Electrical circuit

ABSTRACT

An electrical circuit including components which cooperate with each other, in which a component of the electrical circuit which is waiting for an action to be carried out by another component, is notified by an acknowledgement signal shortly before the implementation of the action that implementation of the action is imminent. The electrical circuit optionally includes a clock generator containing a master clock generator, a clock control unit and several clock signal producing units. The master clock generator produces a master clock signal which is supplied to all of the clock signal producing units. The clock control unit produces several release signals that are respectively supplied to each clock signal producing unit. Each clock signal producing unit passes part of the master clock signal in response to the received release signal, and transfers the passed signal as a clock signal to at least one component of the electrical circuit.

FIELD OF THE INVENTION

The present invention relates to an electrical circuit with componentswhich cooperate with one another.

BACKGROUND OF THE INVENTION

In electrical circuits such as these, the components which cooperatewith one another frequently do not have the same performance, and inparticular they do not operate at the same speed.

One electrical circuit in which this is frequently the case is, by wayof example but as is known by no means exclusively, a programmable unitsuch as a microcontroller.

FIG. 1 shows the fundamental design of a microcontroller. Theillustrated microcontroller contains a core C, memory devices S1 to Snwhich are connected to the core C via a first bus BUS1, and peripheryunits P1 to Pn which are connected to the core C via a second bus BUS2.

The memory devices S1 to Sn are, for example, a RAM, a ROM, a flashmemory, etc.

The periphery units are, for example, an A/D converter a DMA controller,a coding device, a CAN controller, etc.

The core C

-   -   reads commands and operands which are stored in the memory        devices S1 to Sn or in an external memory device which is        provided outside the microcontroller, and carries out these        commands and operands,    -   and in the process cooperates in a predetermined manner with the        memory devices S1 to Sn and with the periphery units P1 to Pn.

Microcontrollers are clock-controlled devices, with the speed at whichthe microcontroller operates (for example how quickly it carries out theprogram to be carried out by it) depending inter alia on the frequencyof the clock signal that is used.

The higher the clock signal frequency, the faster the microcontrolleroperates.

On the other hand, however, high clock signal frequencies lead to a highpower consumption and to the disadvantages associated with this such assevere heating, as well as the production of electromagnetic radiation,etc.

In order to keep these disadvantages within bounds, efforts are beingmade to ensure that the various components of the microcontroller eachrun only as fast as is necessary for correct operation of themicrocontroller. This is generally achieved by producing a number ofclock signals at different frequencies in the microcontroller, and bysupplying these different clock signals to the various components. Thismakes it possible, for example, to supply the core C with a veryhigh-frequency clock signal, and to supply specific periphery units,such as a D/A converter, with a clock signal at a lower clock frequency,for example with a clock signal at half the clock frequency.

However, the fact that certain components of the microcontroller aresupplied with a clock signal at a lower frequency influences not onlythe relevant components themselves but can also influence componentswhich are supplied with a clock signal at a high frequency. This is thecase, for example, when a component which operates at a high clockfrequency, that is to say by way of example the core C, wishes totransmit data to a component which is operating at a lower clockfrequency, for example to the D/A converter. In this case, the core Cmust produce the data to be transmitted for a longer time at its outputsthan would be the case if the receiver of the data were a componentwhich was operating at the same clock frequency as the core C. This isdue to the fact that the clock edges by means of which the D/A convertercan accept data occur at comparatively long time intervals, and becausethe core C must furthermore continue to provide the data to betransferred until the D/A converter has acknowledged correct receptionof the data, in which case the acknowledgement process also takes acertain amount of time owing to the necessity to synchronize the coreand the D/A converter by means of flipflops or the like which arearranged between them. The core C can thus be blocked for a greater orlesser time as a result of which, overall, it operates more slowly thanwould be possible on the basis of its clock frequency.

At least some of the problems which have been mentioned can be overcomeby operating the components alternately using clock signals at differentfrequencies. However, the production of clock signals at differentfrequencies and passing these clock signals to the components that usethem are associated with a high degree of complexity, and are likewisealso associated with considerable disadvantages.

SUMMARY OF THE INVENTION

The present invention is therefore directed to methods and structuresfor carrying out the operation and/or the cooperation between thecomponents of an electrical circuit more efficiently and in a simplermanner than has been the case until now.

The electrical circuit according to the invention is distinguished

-   -   in that a component of the electrical circuit, which is waiting        for the carrying out of an action to be carried out by another        component, is signaled by means of an acknowledgement signal        shortly before the carrying out of the relevant action that the        carrying out of the action is imminent, and/or    -   in that the electrical circuit contains a clock generator for        production of clock signals for the components of the electrical        circuit, with this clock generator containing a master clock        generator, a clock control device and two or more clock signal        generating devices, and with    -   the master clock generator producing a master clock signal and        supplying this to all the clock signal generating devices,    -   the clock control device producing two or more enable signals,        and each clock signal generating device being supplied with an        enable signal, and    -   each of the clock signal generating devices allowing a        proportion of the master clock signal which is governed by the        enable signal to pass, and this signal being passed on as the        clock signal to one or more components of the electrical        circuit.

Since acknowledgement signals which signal that a respective action willbe carried out even before it is carried out are used, the time which acomponent which is waiting for this action to be carried out has to waitcan be reduced to the minimum necessary time.

The clock signal production allows the required clock signals to beproduced and changed particularly easily. Furthermore, it is possiblewith particularly little complexity to ensure that where they are used,that is to say in each of the components in the electrical circuit, theclock signals have a specific phase angle with respect to the clocksignals that are used by each of the other components.

Advantageous developments of the invention are described in thedependent claims, in the following description and in the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in the following text using an exemplaryembodiment and with reference to the figures, in which:

FIG. 1 shows the basic design of a known electrical circuit withcomponents which cooperate with one another,

FIG. 2 shows the design of the electrical circuit which will bedescribed in more detail in the following text,

FIG. 3 shows the design of a clock signal generating device for theelectrical circuit shown in FIG. 2,

FIG. 4 shows the time profile of the output signals of a master clockgenerator, of a clock control device, and of the clock signal generatingdevices for the electrical circuit shown in FIG. 2, and

FIG. 5 shows the design of an acknowledgement signal generator for theelectrical circuit shown in FIG. 2.

DESCRIPTION OF A PREFERRED EXEMPLARY EMBODIMENT

The electrical circuit which is described in the following text is aclock-controlled electrical circuit, to be more precise a programmableunit such as a microcontroller, a microprocessor or a signal processor.

However, it should be mentioned even at this point that the specialfeatures of the programmable unit which are described in the followingtext can also be used for any other electrical circuits with componentswhich cooperate with one another.

The design of the programmable unit described in the following text isillustrated in FIG. 2.

The programmable unit which is shown in FIG. 2 contains:

-   -   a core C,    -   memory devices S1 to Sn which are connected to the core C via a        first bus BUS1,    -   peripheral units P1 to Pn which are connected to the core C via        a second bus BUS2,    -   a large number of clock signal generating devices CGC,    -   a clock generator MCG, which is referred to in the following        text as a master clock generator,    -   a clock control device CEG, and    -   an acknowledgement signal generator QSG.

The programmable unit which is shown in FIG. 2 essentially operates inthe same way as the programmable unit shown in FIG. 1. This means thatthe core C

-   -   reads commands and operands which are stored in the memory        devices S1 to Sn or in an external memory device which is        provided outside the microcontroller, and carries out these        commands and operands,    -   and in the process cooperates in a predetermined manner with the        memory devices S1 to Sn and with the periphery units P1 to Pn.

In contrast, the differences are the way in which the individualcomponents of the programmable unit are supplied with clock signals, andthe way in which the individual components of the programmable unitcooperate with one another.

In the example under consideration, the core C, the memory device S1,the memory device Sn, the peripheral unit P1, and the peripheral unit Pnoperate with clock signals at a different frequency, and each of thecomponents which have been mentioned has its own associated clock signalgenerating device CGC. Components which operate with clock signals atthe same frequency may have a single associated common clock signalgenerating device CGC, particularly if the relevant components arelocated close to one another; components which operate with a clocksignal whose frequency is the same as the frequency of the clock signalwhich is produced by the master clock generator MCG do not require theirown clock signal generator device CGC and make direct use of the clocksignal which is produced by the master clock generator MCG.

The individual components of the programmable unit are supplied withclock signals by the master clock generator MCG, by the clock controldevice CEG and by the clock signal generator devices CGC.

The master clock generator MCG produces a master clock signal m_clkwhich is supplied to all the clock signal generating devices CGC and tothe clock control device CEG. This master clock signal m_clk is asquare-wave signal at a predetermined constant frequency. This masterclock signal m_clk is distributed in such a way that it preferably hasthe same phase angle in all the components to which it is supplied, butat least in those clock signal generating devices CGC which areassociated with components of the programmable unit which cooperate withone another, taking into account the acknowledgement signals which willbe described in more detail later.

The clock signal generating devices CGC are furthermore each suppliedwith a signal which is produced by the clock control device CEG andwhich is referred to in the following text as an enable signal, to beprecise,

-   -   an enable signal clk_en_div_1 is supplied to the clock signal        generating device CGC which is associated with the core C,    -   an enable signal clk_en_div_2 is supplied to the clock signal        generating device CGC which is associated with the memory device        S1,    -   an enable signal clk_en_div_4 is supplied to the clock signal        generating device CGC which is associated with the memory device        Sn,    -   an enable signal clk_en_div_8 is supplied to the clock signal        generating device CGC which is associated with the peripheral        unit P1, and    -   an enable signal clk_en_div_16 is supplied to the clock signal        generating device CGC which is associated with the peripheral        unit Pn.

The clock signal generating devices CGC use the signals which aresupplied to them to produce clock signals which are supplied to thecomponents which are associated with the respective clock signalgenerating devices CGC and are used by them as clock signals.

In this case:

-   -   the clock signal generating device CGC which is associated with        the core C uses the signals m_clk and clk_en_div_1 which are        supplied to it to produce a clock signal clk_div_1 which        corresponds to the master clock signal m_clk,    -   the clock signal generating device CGC which is associated with        the memory device S1 uses the signals m_clk and clk_en_div_2        which are supplied to it to produce a clock signal clk_div_2        whose frequency is half as great as the frequency of the master        clock signal m_clk,    -   the clock signal generating device CGC which is associated with        the memory device Sn uses the signals m_clk and clk_en_div_4        which are supplied to it to produce a clock signal clk_div_4        whose frequency is one quarter of the frequency of the master        clock signal m_clk,    -   the clock signal generating device CGC which is associated with        the peripheral unit P1 uses the signals m_clk and clk_en_div_8        which are supplied to it to produce a clock signal clk_div_8        whose frequency is one eighth of the frequency master clock        signal m_clk, and    -   the clock signal generating device CGC which is associated with        the peripheral unit Pn uses the signals m_clk and clk_en_div_16        which are supplied to it to produce a clock signal clk_div_16        whose frequency is one sixteenth of the frequency of the master        clock signal m_clk.

For the sake of completeness, it should be mentioned that there is noneed to supply the core C with the clock signal clk_div_1, to supply thememory device S1 with the clock signal clk_div_2, to supply the memorydevice Sn with the clock signal clk_div_4, to supply the peripheral unitP1 with the clock signal clk_div_8 and to supply the peripheral unit Pnwith the clock signal clk_div_16; in principle, each of the componentsof the programmable unit may be supplied with any desired clock signalfrom the clock signals clk_div_1, clk_div_2, clk_div_4, clk_div_8, andclk_div_16, to be precise irrespective of which clock signals aresupplied to each of the other components.

Furthermore, there is no restriction to the frequencies of the clocksignals clk_div_1, clk_div_2, clk_div_4, clk_div_8, and clk_div_16 eachdiffering by a factor of 2. The magnitude ratios of the frequencies ofthe clock signals clk_div_1, clk_div_2, clk_div_4, clk_div_8, andclk_div_16 may in principle assume any desired values independently ofone another. However, it is preferable for the components of theprogrammable unit which may be connected to one another to be suppliedwith clock signals which are produced in such a way that thecorresponding edge occurs at the time at which an edge occurs in oneclock signal, even in the clock signals which are at the same frequencyor at a higher frequency. This makes it possible in a particularlysimple manner to allow the components of the programmable unit tocooperate using acknowledgement signals which will be described in moredetail later.

The clock signal generating devices CGC and the components of theprogrammable unit which use the clock signals that are produced by themare arranged such that there are no delay time differences, or at worsenegligibly small delay time differences, during the transmission of theclock signals that are produced by the clock signal generating devicesto the respectively associated components.

The enable signals which are emitted from the clock control device CEG

-   -   in each case suddenly change from the level 0 to the level 1 one        clock period of the master clock signal m_clk before the time at        which the signal that is produced by the clock signal generating        devices CGC is intended to have a rising edge, and    -   maintain this state for a time which corresponds to the duration        of one clock period of the signal m_clk and then suddenly change        back to the level 0.

FIG. 3 shows the design of a clock signal generating device CGC whichcontains a latch element L and an AND gate AND. As its input signal, thelatch element L receives the enable signal clk_en_div_x that is emittedfrom the clock control device CEG, and accepts this with the rising edgeof the master clock signal m_clk. The AND gate AND receives as its inputsignals the output signal from the latch element L and the master clocksignal m_clk, subjects these signals to an AND operation, and in theprocess produces the output signal clk_div_x from the clock signalgenerating device CGC.

The time profiles of the signals mentioned above are illustrated in FIG.4.

As is evident from the explanatory notes above, the various clocksignals clk_div_x are produced by selectively masking out specificsections of the master clock signal m_clk. Therefore, and because thismaster clock signal m_clk is supplied in such a way that it has the samephase angle in all of the components to which it is supplied, that is tosay in all of the clock signal generating devices CGC, and because thereare no delay time differences, or in any case no significant delay timedifferences, during the transmission of the clock signals clk_div_x tothe components which use them, the components of the programmable unitwhich are supplied with the clock signals clk_div_x operate completelysynchronously in all circumstances. This is true even when one, two ormore or all of the enable signals clk_en_div_x which are emitted fromthe clock control device CEG are shifted backwards in time as a resultof problems in the production and/or as a result of different delaytimes within the programmable unit. As is evident from the design of theclock signal generating devices CGC illustrated in FIG. 3 and describedwith respect to this figure, changes in the clock signals clk_div_xwhich are produced by the clock signal generating devices CGC occur onlywhen the enable signals clk_en_div_x which are emitted from the clockcontrol device CEG are shifted backwards by a time which corresponds toone clock period of the master clock signal m_clk, or more.

Irrespective of this, the frequencies of the clock signals clk_div_x canbe changed very easily at any time, even during operation of theprogrammable unit. All that is necessary to do this is to appropriatelymodify the enable signals clk_en_div_x (which govern the frequencies ofthese signals) for the clock control device CEG.

The enable signals clk_en_div_x may be produced using counters whichcount the clock periods of the master clock signal m_clk and initiatechanges to the level of the enable signals clk_en_div_x when specificcounts are reached. In consequence, the frequencies of the clock signalsclk_div_x can be changed simply by appropriate readjustment of thecounters, and the timing of the enable signals clk_en_div_x can onceagain also be varied within certain limits in this case.

The enable signals clk_en_div_x which are emitted by the clock controldevice CEG are also supplied to the acknowledgement signal generatorQSG.

The acknowledgement signal generator QSG is also supplied with chipselect signals which are annotated cs1 to cs4. The chip select signalsare signals which the core C outputs and which are supplied to thememory device S1 (chip select signal cs1), to the memory device Sn (chipselect signal cs2), to the peripheral unit P1 (chip select signal cs3)and to the peripheral unit Pn (chip select signal cs4) via separatelines (which are not part of the buses BUS1 and BUS2), in order tosignal to them that the core C wishes to communicate with the respectiverelevant unit.

The acknowledgement signal generator QSG uses the signals supplied to itto form acknowledgement signals q1 to q4, which are supplied to the coreC.

FIG. 5 shows the design of the acknowledgement signal generator, whichcomprises AND gates AND1 to AND4, with

-   -   the AND gate AND1 subjecting the chip select signal cs1 which is        associated with the memory device S1 and the enable signal        clk_en_div_2 which is associated with the memory device S1 to        AND linking, and using the signal which results from this as the        acknowledgement signal q1, which is output to the core C    -   the AND gate AND2 subjecting the chip select signal cs2 which is        associated with the memory device Sn and the enable signal        clk_en_div_4 which is associated with the memory device Sn to        AND linking, and using the signal which results from this as the        acknowledgement signal q2, which is output to the core C    -   the AND gate AND3 subjecting the chip select signal cs3 which is        associated with the peripheral unit P1 and the enable signal        clk_en_div_8 which is associated with the peripheral unit P1 to        AND linking, and using the signal which results from this as the        acknowledgement signal q3, which is output to the core C, and    -   the AND gate AND4 subjecting the chip select signal cs4 which is        associated with the peripheral unit Pn and the enable signal        clk_en_div_16 which is associated with the peripheral unit Pn to        AND linking, and using the signal which results from this as the        acknowledgement signal q4, which is output to the core C.

In consequence, the core C

-   -   is signaled by the acknowledgement signal q1 that the occurrence        of a rising edge in the clock signal which is used by the memory        device S1 is imminent,    -   is signaled by the acknowledgement signal q2 that the occurrence        of a rising edge in the clock signal which is used by the memory        device Sn is imminent,    -   is signaled by the acknowledgement signal q3 that the occurrence        of a rising edge in the clock signal which is used by the        peripheral unit P1 is imminent, and    -   is signaled by the acknowledgement signal q4 that the occurrence        of a rising edge in the clock signal which is used by the        peripheral unit Pn is imminent.

If the core C is actually waiting for the component selected by one ofthe chip select signals to carry out a specific action when the nextrising edge occurs, then the core C can use the acknowledgement signalas advanced confirmation of this action being carried out, and can endthe waiting process.

The advantages of this procedure can be illustrated by an example:

Let us assume that the core C wishes to transmit data to the peripheralunit P1. In this situation, the core C signals to the peripheral unit P1via the chip select signal cs3 that the core C wishes to communicatewith it via the bus BUS2, and applies the data to be transmitted to theperipheral unit P1 to the bus BUS2. The peripheral unit P1 can acceptthis data on the next rising clock edge of the clock signal clk_div_8which is used by it. Let us assume that this rising edge coincides withthe rising edge of the clock cycle No.n of the clock signal m_clk whichis used by the core. The core C then in fact receives theacknowledgement signal q3 in the clock cycle No. n-1. Theacknowledgement signal q3 signals to the core C that the data outputfrom it on the bus will be accepted by the peripheral unit in the nextclock cycle, that is to say in the clock cycle No. n. The core C canthus in fact end the outputting of the data at the start of the clockcycle No. n, and can continue to carry out the program.

In the case of a conventional programmable unit, for example in the caseof the programmable unit illustrated in FIG. 1 and already described inthe introduction with reference to this figure, the outputting of thedata to be transmitted to the peripheral unit P1 would have to becontinued for a longer period, to be more precise would have to becontinued until the peripheral unit has confirmed reception of the data.

It should be evident and requires no further explanation that thegeneration and use of acknowledgement signals as described above is alsoadvantageous in other situations in which the core C is waiting for aspecific action to be carried out by one of the memory devices orperipheral units.

The core C can operate more quickly by the generation and use of theacknowledgement signals and, furthermore, there is no need for thecomponents of the programmable unit which are communicating with oneanother to carry out a handshake process.

It may also be found to be advantageous for the peripheral units and/orthe memory devices also to be supplied with appropriate acknowledgementsignals, to be more precise with the enable signal clk_en_div_x for thatcomponent with which the relevant peripheral unit or memory device iscurrently communicating. The generation and use of acknowledgementsignals has always been found to be advantageous when the component towhich it is being supplied uses a clock of the same speed as or which isfaster than the component with which it is currently communicating.

It should be evident that the way in which the acknowledgement signalsare generated and used may be modified in many ways.

For example, it would be possible to provide for the number ofacknowledgement signals to be minimized. In the example underconsideration, it would be possible in this case, for example, tosubject the acknowledgement signals q1 and q2 and the acknowledgementsignals q3 and q4 to an OR logic operation, and to use the results ofthe OR logic operations as acknowledgement signals. This would thenresult in there being only two acknowledgement signals instead of four.This reduction in the number of acknowledgement signals is notdisadvantageous in the example under consideration because the twoperipheral units can never communicate with the core at the same time,and because the two memory devices can never communicate with the coreat the same time either.

It would also be possible to dispense with the acknowledgement signalgenerator QSG and to supply the core, the peripheral units and/or thememory devices directly with the enable signals clk_en_div_x for each ofthe other components with which they can communicate.

The special features described above allow the operation and/or thecooperation of components in an electrical circuit to be carried outconsiderably more efficiently, and in a simple manner, than is the casewith conventional electrical circuits.

LIST OF REFERENCE SYMBOLS

-   AND AND gate-   BUSx Bus-   C Core-   CEG Clock control device-   CGC Clock signal generating device-   clk_div_x Output signal from CGC; clock signal-   clk_en_div_x Output signal from CEG; enable signal-   csx Chip select signal-   L Latch element-   MGC Master clock generator-   m_clk Output signal from MCG; master clock signal-   Px Periphery units-   qx Acknowledgement signal-   QSG Acknowledgement signal generator-   Sx Memory devices

1. An electrical circuit comprising: a plurality of components whichcooperate with one another, and means for signaling a first component ofthe electrical circuit, which is waiting for a second component of theelectrical circuit to perform an action, by producing an acknowledgementsignal shortly before the performance of the action indicating that theperformance of the action is imminent.
 2. The electrical circuit asclaimed in claim 1, wherein the components of the electrical circuit areclock-controlled components.
 3. The electrical circuit as claimed inclaim 2, wherein at least some of the components of the electricalcircuit operate with different clock signals.
 4. The electrical circuitas claimed in claim 3, wherein the clock signal, with which thecomponent which is carrying out the action operates is at the same or alower frequency than the clock signal with which the component which iswaiting for the action to be carried out operates.
 5. The electricalcircuit as claimed in claim 2, wherein the acknowledgement signal isproduced during the period of the clock signal which is used by thewaiting component, within which period or following which period theaction which is being waited for by the waiting component is carriedout.
 6. The electrical circuit as claimed in claim 2, wherein theacknowledgement signal is produced during the period of the clock signalwhich is used by the waiting component, within which period or followingwhich period the flank of the clock signal which is used by thecomponent which is carrying out the action occurs, and on whoseoccurrence the action is carried out.
 7. The electrical circuit asclaimed in claim 2, wherein the acknowledgement signal is producedtaking into account a signal on the basis of which the clock signal isproduced, which is used by the component which is carrying out theaction.
 8. The electrical circuit as claimed in claim 7, wherein theacknowledgement signal is produced by logic linking of the signal, onthe basis of which the clock signal is produced, which is used by thecomponent which is carrying out the action, and a selection signal isproduced which supplies the component which is waiting for the action tothe component which is carrying out this action in order to signal to itthat the component which is waiting for the action wishes to communicatewith this component which is carrying out this action.
 9. The electricalcircuit as claimed in claim 1, wherein the first component which iswaiting for the action to be carried out uses the acknowledgement signalas confirmation that the action which is being waited for has beencarried out.
 10. The electrical circuit as claimed in claim 1, whereinthe component which is waiting for the action to be carried out ends thewaiting for the action in the clock period of the clock signal which isused by this component and which follows the period within which therelevant component is supplied with the acknowledgement signal.
 11. Theelectrical circuit as claimed in claim 1, wherein the acknowledgementsignal is formed by a component of the electrical circuit which is notidentical to the component which is carrying out the action whosecompletion is being waited for.
 12. The electrical circuit as claimed inclaim 1, wherein the electrical circuit contains a clock generator forproduction of clock signals for the components of the electricalcircuit, with this clock generator containing a master clock generator,a clock control device and two or more clock signal generating devices,and with the master clock generator producing a master clock signal andsupplying this to all the clock signal generating devices, the clockcontrol device producing two or more enable signals and each clocksignal generating device being supplied with an enable signal, and eachof the clock signal generating devices allowing a proportion of themaster clock signal which is governed by the enable signal to pass, andthis signal being passed on as the clock signal to one or morecomponents of the electrical circuit.
 13. The electrical circuit asclaimed in claim 12, wherein the master clock signal is supplied to theclock signal generating devices such that it reaches all of the clocksignal generating devices with the same phase angle.
 14. The electricalcircuit as claimed in claim 12, wherein the enable signal which isproduced by the clock control device is at a different level for acertain time than would otherwise be the case before the time at whichthe clock signal that is to be produced taking into account this enablesignal is intended to have a specific edge.
 15. The electrical circuitas claimed in claim 12, wherein the clock signal generating devices eachcontain a latch element and an AND gate, with the latch elementaccepting the instantaneous level of the enable signal with the risingedge of the master clock signal, with the AND gate carrying out ANDlinking of the output signal from the latch element and of the masterclock signal, and with the output signal from the AND gate being used asthe clock signal which is to be produced by the clock signal generatingdevice.
 16. The electrical circuit as claimed in claim 12, wherein theacknowledgement signal is formed taking into account the enable signal.17. The electrical circuit as claimed in claim 1, wherein the electricalcircuit is an integrated circuit.
 18. The electrical circuit as claimedin claim l,wherein the electrical circuit is a programmable unit. 19.The electrical circuit as claimed in claim 18, wherein the component ofthe programmable unit to which the acknowledgement signal is supplied isthe core of the programmable unit.
 20. An electrical circuit comprising:a plurality of components which cooperate with one another, a clockgenerator for production of clock signals for the components of theelectrical circuit, wherein this clock generator includes a master clockgenerator, a clock control device and two or more clock signalgenerating devices, and wherein the master clock generator produces amaster clock signal and supplies the master clock signal to all of theclock signal generating devices, the clock control device produces twoor more enable signals, and each clock signal generating device issupplied with an enable signal, and each of the clock signal generatingdevices includes means for allowing a proportion of the master clocksignal which is governed by the enable signal to pass, wherein thissignal is passed on as the clock signal to one or more components of theelectrical circuit.
 21. The electrical circuit as claimed in claim 20,wherein the master clock signal is supplied to the clock signalgenerating devices such that it reaches all of the clock signalgenerating devices with the same phase angle.
 22. The electrical circuitas claimed in claim 20, wherein the enable signal which is produced bythe clock control device is at a different level for a certain time thanwould otherwise be the case before the time at which the clock signalthat is to be produced taking into account this enable signal isintended to have a specific edge.
 23. The electrical circuit as claimedin claim 20, wherein the clock signal generating devices each contain alatch element and an AND gate, with the latch element accepting theinstantaneous level of the enable signal with the rising edge of themaster clock signal, with the AND gate carrying out AND linking of theoutput signal from the latch element and of the master clock signal, andwith the output signal from the AND gate being used as the clock signalwhich is to be produced by the clock signal generating device.
 24. Theelectrical circuit as claimed in claim 20, wherein a component of theelectrical circuit, which is waiting for the carrying out of an actionto be carried out by another component, is signaled by means of anacknowledgement signal shortly before the carrying out of the relevantaction that the carrying out of the action is imminent.
 25. Theelectrical circuit as claimed in claim 24, wherein the components of theelectrical circuit are clock-controlled components.
 26. The electricalcircuit as claimed in claim 25, wherein at least some of the componentsof the electrical circuit operate with different clock signals.
 27. Theelectrical circuit as claimed in claim 26, wherein the clock signal withwhich the component which is carrying out the action operates is at thesame or a lower frequency than the clock signal with which the componentwhich is waiting for the action to be carried out operates.
 28. Theelectrical circuit as claimed in claim 25, wherein the acknowledgementsignal is produced during the period of the clock signal which is usedby the waiting component, within which period or following which periodthe action which is being waited for by the waiting component is carriedout.
 29. The electrical circuit as claimed in claim 25, wherein theacknowledgement signal is produced during the period of the clock signalwhich is used by the waiting component, within which period or followingwhich period the flank of the clock signal which is used by thecomponent which is carrying out the action occurs, and on whoseoccurrence the action is carried out.
 30. The electrical circuit asclaimed in claim 25, wherein the acknowledgement signal is producedtaking into account a signal on the basis of which the clock signal isproduced, which is used by the component which is carrying out theaction.
 31. The electrical circuit as claimed in claim 30, wherein theacknowledgement signal is produced by logic linking of the signal, onthe basis of which the clock signal is produced, which is used by thecomponent which is carrying out the action, and a selection signal isproduced which supplies the component which is waiting for the action tothe component which is carrying out this action in order to signal to itthat the component which is waiting for the action wishes to communicatewith this component which is carrying out the action.
 32. The electricalcircuit as claimed in claim 24, wherein the component which is waitingfor the action to be carried out uses the acknowledgement signal asconfirmation that the action which is being waited for has been carriedout.
 33. The electrical circuit as claimed in claim 24, wherein thecomponent which is waiting for the action to be carried out ends thewaiting for the action in the clock period of the clock signal which isused by this component and which follows the period within which therelevant component is supplied with the acknowledgement signal.
 34. Theelectrical circuit as claimed claim 24, wherein the acknowledgementsignal is formed by a component of the electrical circuit which is notidentical to the component which is carrying out the action whosecompletion is being waited for.
 35. The electrical circuit as claimed inclaim 24, wherein the acknowledgement signal is formed taking account ofthe enable signal.
 36. The electrical circuit as claimed in claim 20,wherein the electrical circuit is an integrated circuit.
 37. Theelectrical circuit as claimed in claim 20, wherein the electricalcircuit is a programmable unit.
 38. The electrical circuit as claimed inclaim 37, wherein the component of the programmable unit to which theacknowledgement signal is supplied is a core of a programmable unit.